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| Ordering number : EN5502 CMOS LSI LC78625E Compact Disc Player DSP Overview The LC78625E is a CMOS LSI that implements the signal processing and servo control required by compact disc players, laser discs, CD-V, CD-I and related products. The LC78625E provides several types of signal processing, including demodulation of the optical pickup EFM signal, de-interleaving, error detection and correction, and digital filters that can help reduce the cost of CD player units. It also processes a rich set of servo system commands sent from the control microprocessor. It also incorporates an EFM-PLL circuit and a one-bit D/A converter. This LSI is an improved version of the LC78620E. In addition to supporting low-voltage operation, on/off control of the de-emphasis function and use of the bilingual function have been enabled in certain additional modes. * Demodulated EFM signal buffering in internal RAM to handle up to 4 frames of disc rotational jitter * Demodulated EFM signal reordering in the prescribed order for data unscrambling and de-interleaving * Error detection, correction, and flag processing (error correction scheme: dual C1 plus dual C2 correction) * The LC78625E sets the C2 flags based on the C1 flags and a C2 check, and then performs signal interpolation or muting depending on the C2 flags. The interpolation circuit uses a quadruple interpolation scheme. The output value converges to the muting level when four or more consecutive C2 flags occur. Package Dimensions unit: mm 3174-QFP80E [LC78625E] Functions * The LC78625E takes an HF signal as input, digitizes (slices) that signal at a precise level, converts that signal to an EFM signal, and generates a PLL clock with an average frequency of 4.3218 MHz by comparing the phases of that signal and an internal VCO. * A precise reference clock and the necessary internal timings are generated using an external 16.9344 MHz crystal oscillator. * Disc motor speed control using a frame phase difference signal generated from the playback clock and the reference clock * Frame synchronization signal detection, protection, and interpolation to assure stable data readout * EFM signal demodulation and conversion to 8-bit symbol data * Subcode data separation from the EFM demodulated signal and output of that data to an external microprocessor * Subcode Q signal output (LSB first) to a microprocessor over the serial interface after performing a CRC error check SANYO: QFP80E SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 22897HA (OT) No. 5502-1/35 LC78625E * Support for command input from a control microprocessor: commands include track jump, focus start, disk motor start/stop, muting on/off and track count (8-bit serial input) * Built-in digital output circuits. * Arbitrary track counting to support high-speed data access * D/A converter outputs with data continuity improved by 8x oversampling digital filters. (These filters function as 4x oversampling filters during double-speed playback.) * Built-in D/A converter implemented by a third-order noise shaper circuit (for PWM output) * Built-in digital attenuator (8 bits - alpha, 239 steps) * Built-in digital de-emphasis circuit that can be controlled externally in some modes * Zero-cross muting * Support for 2x-speed dubbing * Support for bilingual applications * General-purpose I/O ports: 4 pins (when the antishock mode is turned off) Features * 5 V single-voltage power supply * Low-voltage operation: Can be operated at 3.3 V 10% (at normal playback speed) * 80-pin QFP package Equivalent Circuit Block Diagram No. 5502-2/35 LC78625E Pin Assignment Specifications Absolute Maximum Ratings at Ta = 25C, VSS = 0 V Parameter Maximum supply voltage Maximum input voltage Maximum output voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD max VIN VOUT Pd max Topr Tstg Conditions Ratings VSS - 0.3 to +7.0 VSS - 0.3 to VDD + 0.3 VSS - 0.3 to VDD + 0.3 300 -20 to +75 -40 to +125 Unit V V V mW C C Allowable Operating Ranges at Ta = 25C, VSS = 0 V Parameter Symbol VDD (1) Supply voltage VDD (2) Conditions VDD, XVDD, LVDD, RVDD, VVDD : At normal playback speed VDD, XVDD, LVDD, RVDD, VVDD : At 2x playback speed DEFI, FZD, ASDACK/P0, ASFIN/P1, ASDEPC/P2, ASLRCK/P3, COIN, RES, HFL, TES, SBCK, RWC, CQCK, TAI, TEST1 to TEST5, DEMO, CS EFMIN DEFI, FZD, ASDACK/P0, ASFIN/P1, ASDEPC/P2, ASLRCK/P3, COIN, RES, HFL, TES, SBCK, RWC, CQCK, TAI, TEST1 to TEST5, DEMO, CS EFMIN COIN, RWC : Figure 1 COIN, RWC : Figure 1 SBCK, CQCK : Figuires 1, 2 and 3 SBCK, CQCK : Figuires 1, 2 and 3 SQOUT, PW : Figuires 2 and 3 Ratings min 3.0 4.5 typ max 5.5 5.5 Unit V V Input high-level voltage VIH (1) VIH (2) 0.7 VDD 0.6 VDD VDD VDD V V Input low-level voltage VIL (1) VIL (2) 0 0.3 VDD 0.4 VDD V 0 400 400 400 400 0 V ns ns ns ns Data setup time Data hold time High-level clock pulse width Low-level clock pulse width Data read access time tSU tHD tWH tWL tRAC 400 ns Continued on next page. No. 5502-3/35 LC78625E Continued from preceding page. Parameter Command transfer time Subcode Q read enable time Subcode read cycle Subcode read enable time Port input data setup time Port input data hold time Port input clock setup time Port output data delay time Input level Operating frequency range Crystal oscillator frequency Symbol tRWC tSQE tSC tSE tPSU tPHD tRCQ tPDD VIN (1) VIN (2) fOP (1) fX RWC : Figure 1 WRQ: Figure 2, with no RWC signal SFSY : Figure 3 SFSY : Figure 3 ASDACK/P0, ASFIN/P1, ASDEPC/P2, ASLRCK/P3, RWC : Figure 4 ASDACK/P0, ASFIN/P1, ASDEPC/P2, ASLRCK/P3, RWC : Figure 4 CQCK, RWC : Figure 4 ASDACK/P0, ASFIN/P1, ASDEPC/P2, ASLRCK/P3, RWC : Figure 5 EFMIN XIN : Capacitor coupled input EFMIN XIN, XOUT : In 16M mode 16.9344 1.0 1.0 10 400 400 400 100 1200 Conditions Ratings min 1000 11.2 136 typ max Unit ns ms s ns ns ns ns ns Vp-p Vp-p MHz MHz Electrical Characteristics at Ta = 25C, VDD = 5 V, VSS = 0 V Parameter Current drain Symbol IDD IIH (1) Input high-level current IIH (2) DEFI, EFMIN, FZD, ASDACK/P0, ASFIN/P1, ASDEPC/P2, ASLRCK/P3, COIN, RES, HFL, TES, SBCK, RWC, CQCK : VIN = 5 V TAI, TEST1 to TEST5, DEMO, CS : VIN = VDD = 5.5 V DEFI, EFMIN, FZD, ASDACK/P0, ASFIN/P1, ASDEPC/P2, ASLRCK/P3, COIN, RES, HFL, TES, SBCK, RWC, CQCK, TAI, TEST1 to TEST5, DEMO, CS : VIN = 0 V EFMO, EFMO, CLV+, CLV-, V/P, FOCS, PCK, FSEQ, TOFF, TGL, THLD, JP+, JP-, EMPH, EFLG, FSX : IOH = -1 mA MUTEL, MUTER, LRCKO, DFORO, DFOLO, DACKO, TST10, ASDACK/P0, ASFIN/P1, ASDEPC/P2, ASLRCK/P3, LRSY, CK2, ROMXA, C2F, SBSY, PW, SFSY, WRQ, SQOUT, TST11, 16M, 4.2M, CONT : IOH = -0.5 mA LASER : IOH = -1 mA DOUT : IOH = -12 mA LCHP, RCHP, LCHN, RCHN : IOH = -1 mA EFMO, EFMO, CLV+, CLV-, V/P, FOCS, PCK, FSEQ, TOFF, TGL, THLD, JP+, JP-, EMPH, EFLG, FSX : IOL = 1 mA MUTEL, MUTER, LRCKO, DFORO, DFOLO, DACKO, TST10, ASDACK/P0, ASFIN/P1, ASDEPC/P2, ASLRCK/P3, LRSY, CK2, ROMXA, C2F, SBSY, PW, SFSY, WRQ, SQOUT, TST11, 16M, 4.2M, CONT, LASER : IOL = 2 mA DOUT : IOL = 12 mA FST : IOL = 5 mA LCHP, RCHP, LCHN, RCHN : IOL = 1 mA PDO, CLV+, CLV-, JP+, JP-, FST : VOUT = 5 V PDO, CLV+, CLV-, JP+, JP- : V PDO : RISET = 68 k PDO : RISET = 68 k OUT = 0 V Conditions Ratings min typ 30 max 45 5 Unit mA A 25 75 A Input low-level current IIL -5 A VOH (1) 4 V Output high-level voltage VOH (2) 4 V VOH (3) VOH (4) VOH (5) VOL (1) 4.6 4.5 3.0 4.5 1 V V V V Output low-level voltage VOL (2) 0.4 V VOL (3) VOL (4) VOL (5) Output off leakage current IOFF (1) IOFF (2) Charge pump output current IPDOH IPDOL 0.5 0.75 0.5 2.0 5 -5 100 -150 125 -125 150 -100 V V V A A A A Note: For guaranteed operation, the VCO oscillator frequency range adjustment resistor FR must be a 1.20 k 5.0% tolerance resistor. No. 5502-4/35 LC78625E One-Bit D/A Converter Analog Characteristics at Ta = 25C, VDD = LVDD = RVDD = 5 V, VSS = LVSS = RVSS = 0 V Parameter Symbol Conditions LCHP, RCHP, LCHN, RCHN; 1 kHz: 0 dB data input, using the 20 kHz low-pass filter (AD725D built in) LCHP, RCHP, LCHN, RCHN; 1 kHz: -60 dB data input, using the 20 kHz low-pass filter and the A filter (AD725D built in) LCHP, RCHP, LCHN, RCHN; 1 kHz: 0 dB data input, using the 20 kHz low-pass filter and the A filter (AD725D built in) LCHP, RCHP, LCHN, RCHN; 1 kHz: 0 dB data input, using the 20 kHz low-pass filter (AD725D built in) 84 Ratings min typ 0.008 max 0.0010 Unit Total harmonic distortion THD + N % Dynamic range DR 88 dB Signal-to-noise ratio S/N 98 100 dB Crosstalk CT 96 98 dB Note: Measured with the normal-speed playback mode digital attenuator in the Sanyo one-bit D/A converter block reference circuit. Figure 1 Command Input Figure 2 Subcode Q Output Figure 3 Subcode Output No. 5502-5/35 LC78625E Figure 4 General-Purpose Port Input Timing Figure 5 General-Purpose Port Output Timing No. 5502-6/35 LC78625E One-Bit D/A Converter Output Block Reference Circuit No. 5502-7/35 LC78625E Pin Functions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Symbol DEFI TAI PDO VVSS ISET VVDD FR VSS EFMO EFMO EFMIN TEST2 CLV+ CLV- V/P FOCS FST FZD HFL TES PCK FSEQ TOFF TGL THLD TEST3 VDD JP+ JP- DEMO TEST4 EMPH LRCKO DFORO DFOLO DACKO TST10 O O I I O O O O O O Digital filter outputs O O I I O O O O O I I I O O O O O I Slice level control AI AI I/O I I O PLL pins Function Defect detection signal (DEF) input (This pin must be connected to 0 V if unused.) Test input. A pull-down resistor is built in. (This pin must be connected to 0 V in normal operation.) External VCO control phase comparator output Internal VCO ground. (This pin must be connected to 0 V.) PDO output current adjustment resistor connection Internal VCO power supply. VCO frequency range adjustment Digital system ground. (This pin must be connected to 0 V.) EFM signal inverted output EFM signal output EFM signal input Test input. A pull-down resistor is built in. This pin must be connected to 0 V in normal operation. Spindle servo control output. Acceleration when CLV+ is high, deceleration when CLV- is high. Three-value output is also possible when specified by microprocessor command. Rough servo/phase control automatic switching monitor output. Outputs a high level during rough servo and a low level during phase control. Focus servo on/off output. Focus servo is on when the output is low. Focus start pulse output. This is an open-drain output. Focus error zero cross signal input. (This pin must be connected to 0 V if unused.) Track detection signal input. This is a Schmitt input. Tracking error signal input. This is a Schmitt input. EFM data playback clock monitor. Outputs 4.3218 MHz when the phase is locked. Synchronization signal detection output. Outputs a high level when the synchronization signal detected from the EFM signal and the internally generated synchronization signal agree. Tracking off output Tracking gain switching output. Increase the gain when low. Tracking hold output Test input. A pull-down resistor is built in. (This pin must be connected to 0 V.) Digital system power supply. Track jump output. A high level output from JP+ indicates acceleration during an outward jump or deceleration during an inward jump. A high level output from JP- indicates acceleration during an inward jump or deceleration during an outward jump. Three-value output is also possible when specified by microprocessor command. Sound output function input used for end product adjustment manufacturing steps. A pull-down resistor is built in. (This pin must be connected to 0 V.) Test input. A pull-down resistor is built in. (This pin must be connected to 0 V.) De-emphasis monitor pin. A high level indicates playback of a de-emphasis disk. Word clock output Right channel data output Left channel data output Bit clock output Test output. Leave open. (Normally outputs a low level.) Continued on next page. No. 5502-8/35 LC78625E Continued from preceding page. Pin No. 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Symbol ASDACK/P0 ASDFIN/P1 ASDEPC/P2 ASLRCK/P3 LRSY CK2 ROMXA C2F MUTEL LVDD LCHP LCHN LVSS RVSS RCHN RCHP RVDD MUTER DOUT SBSY EFLG PW SFSY SBCK FSX WRQ RWC SQOUT COIN CQCK RES TST11 LASER 16M 4.2M CONT TEST5 CS XVSS XIN XOUT XVDD TEST1 I I O Connections for a 16.9344 MHz crystal oscillator Crystal oscillator power supply Test input. A pull-down resistor is built in. (This pin must be connected to 0 V.) O O O O O O I O O I O I I I O O O O O I I Digital output Subcode block synchronization signal output C1, C2, single and double error correction monitor pin Subcode P, Q, R, S, T, U and W output Subcode frame synchronization signal output. This signal falls when the subcodes are in the standby state. Subcode readout clock input. This is a Schmitt input. (This pin must be connected to 0 V if unused.) Output for the 7.35 kHz synchronization signal divided from the crystal oscillator Subcode Q output standby output Read/write control input. This is a Schmitt input. Subcode Q output Command input from the control microprocessor Input for the command input acquisition clock or the SQOUT pin subcode readout clock input. This is a Schmitt input. Reset input. This pin must be set low briefly after power is first applied. Test output. Leave open. (Normally outputs a low level.) Laser on/off output. Controlled by serial data commands from the control microprocessor. 16.9344 MHz output 4.2336 MHz output Supplementary control output. Controlled by serial data commands from the control microprocessor. Test input. A pull-down resistor is built in. (This pin must be connected to 0 V.) Chip select input. A pull-down resistor is built in. This pin must be connected to 0 V if unused. Crystal oscillator ground. Must be connected to 0 V. O O O O One-bit D/A converter signals I/O I/O * When antishock mode is not used, these pins are used as generalI/O purpose I/O ports (P0 to P3). They must either be set to input mode and I/O connected to 0 V, or set to output mode and left open, if unused. I/O O O ROMXA application output signals O O O Function Bit clock input Left and right channel data input The antishock inputs in antishock mode. Sets the built-in de-emphasis filter on or off. (High: on, low: off) L/R clock input L/R clock output Bit clock output (after reset) Interpolation data output (after reset) C2 flag output Left channel mute output Left channel power supply Left channel P output Left channel N output Left channel ground. Must be connected to 0 V. Right channel ground. Must be connected to 0 V. Right channel N output Right channel P output Right channel power supply Right channel mute output Inverted polarity clock output (during CK2CON mode) ROM data output (during ROMXA mode) Note: All power-supply pins (VDD, VVDD, LVDD, RVDD, and XVDD) must be connected to the same potential. No. 5502-9/35 LC78625E CD System Block Diagrams Pin Applications 1. HF signal input circuit; Pin 11: EFMIN, pin 10: EFMO, pin 9: EFMO, pin 1: DEFI, pin 13: CLV+ An EFM signal (NRZ) sliced at an optimal level can be acquired by inputting the HF signal to EFMIN. The LC78625E handles defects as follows. When a high level is input to the DEFI pin (pin 1), the EFMO (pin 9) and EFMO (pin 10) pins (the slice level control outputs) go to the high-impedance state, and the slice level is held. However, note that this function is only valid in CLV phase control mode, that is, when the V/P pin (pin 15) is low. This function can be used in combination with the LA9230/40 series DEF pin. Note: If the EFMIN and CLV+ signal lines are too close to each other, unwanted adiation can result in error rate degradation. We recommend laying a ground or VDD shield line between these two lines. 2. PLL clock generation circuit; Pin 3: PDO, pin 5: ISET, pin 7: FR, pin 21: PCK Since the LC78625E includes a VCO circuit, a PLL circuit can be formed by connecting an external RC circuit. ISET is the charge pump reference current, PDO is the VCO circuit loop filter, and FR is a resistor that determines the VCO frequency range. (Reference values) R1 = 68 k, C1 = 0.1 F R2 = 680 k, C2 = 0.1 F R3 = 1.2 k Note: We recommend using a 5.0% tolerance carbon film resistor for R3. No. 5502-10/35 LC78625E 3. VCO monitor; Pin 21: PCK PCK is a monitor pin that outputs an average frequency of 4.3218 MHz, which is the VCO frequency divided by two. 4. Synchronization detection monitor; Pin 22: FSEQ Pin 22 goes high when the frame synchronization (a positive polarity synchronization signal) from the EFM signal read in by PCK and the timing generated by the counter (the interpolation synchronization signal) agree. This pin is thus a synchronization detection monitor. (It is held high for a single frame.) 5. Servo command function; Pin 64: RWC, pin 66: COIN, pin 67: CQCK Commands can be executed by setting RWC high and inputting commands to the COIN pin in synchronization with the CQCK clock. Note that commands are executed on the falling edge of RWC. Focus start Track jump Muting control Disc motor control Miscellaneous control Track check Digital attenuator General-purpose port I/O data setup * One-byte commands One byte commands Two-byte command (RWC set twice) Two-byte commands (RWC set once) * Two-byte commands (RWC set twice) * Two-byte commands (RWC set once) No. 5502-11/35 LC78625E * Command noise rejection Code $EF $EE COMMAND Command input noise reduction mode Reset the above mode. q RES = L This command reduces the noise on the CQCK clock signal. While this is effective for noise pulses shorter than 500 ns, the CQCK timings tWL, tWH, and tSU (see page 5, figures 1 and 2), must be set to be at least 1 s. 6. Focus servo circuit; Pin 16: FOCS, pin 17: FST, pin 18: FZD, pin 70: LASER Code $08 $A2 $0A $8A $FE COMMAND FOCUS START #1 FOCUS START #2 LASER ON LASER OFF NOTHING q RES = L The FOCS, FST, and FZD pins are not required when the LC78625E is used in combination with an LA9230/40 Series LSI. FZD should be connected to 0 V when these pins are not used. The LA9230/40 Series focus start command is identical to the LC78625E FOCUS START #1 command. * NOTHING This command can be used to initialize the LC78625E by inputting FE (hexadecimal: Hexadecimal constants are written with a dollar sign ($) prefix). Note that $00 is the reset command for the LA9230/40 Series, and should be used with care since it clears the result of the automatic adjustment process and returns these chips to their initial states. * Laser control The LASER pin can be use as an extended output port. * Focus start When the LC78625E is used in combination with an LA9230/40 Series LSI, the focus start operation is executed completely on the servo side by commands from the control microprocessor. The following section describes this operation when the LC78625E is used in combination with an LA9210M or LA9211M. When a focus start instruction (either FOCUS START #1 or FOCUS START #2) is input as a servo command, first the charge on capacitor C1 is discharged by FST and the objective lens is lowered. Next, the capacitor is charged by FOCS, and the lens is slowly raised. FZD falls when the lens reaches the focus point. When this signal is received, FOCS is reset and the focus servo turns on. After sending the command, the microprocessor should check the in-focus detection signal (the LA9210 DRF signal) to confirm focus before proceeding to the next part of the program. If focus is not achieved by the time C1 is fully charged, the microprocessor should issue another focus command and iterate the focus servo operation. No. 5502-12/35 LC78625E Note:* Values in parentheses are for the FOCUS START #2 command. The only difference is in the FST low period. * An FZD falling edge will not be accepted during the period that FST is low. * After issuing a focus start command, initialization will be performed if RWC is set high. Therefore, do not issue the next command during focus start until the focus coil drive S curve has completed. * When focus cannot be achieved (i.e., when FZD does not go low) the FOCS signal will remain in the high state and the lens will remain raised, so the microprocessor should initialize the system by issuing a NOTHING command. * When the RES pin is set low, the LASER pin is set high directly. * Focus start using the DEMO pin executes a mode #1 focus start. No. 5502-13/35 LC78625E 7. CLV servo circuit; Pin 13: CLV+, pin 14: CLV-, pin 15: V/P Code $04 $05 $06 $07 COMMAND DISC MOTOR START (accelerate) DISC MOTOR CLV (CLV) DISC MOTOR BRAKE (decelerate) DISC MOTOR STOP (stop) q RES = L The CLV+ pin provides the signal that accelerates the disk in the forward direction and the CLV- pin provides the signal that decelerates the disk. Commands from the control microprocessor select one of the four modes accelerate, decelerate, CLV and stop. The table below lists the CLV+ and CLV- outputs in each of these modes. Mode Accelerate Decelerate CLV Stop CLV+ H L Pulse output L CLV- L H Pulse output L Note: * CLV servo control commands can set the TOFF pin low only in CLV mode. That pin will be at the high level at all other times. Control of the TOFF pin by microprocessor command is only valid in CLV mode. * CLV mode In CLV mode the LC78625E detects the disk speed from the HF signal and provides proper linear speed using several different control schemes by switching the DSP internal modes. The PWM period corresponds to a frequency of 7.35 kHz. The V/P pin outputs a high level during rough servo and a low level during phase control. Internal Mode Rough servo (When determined to be under speed) Rough servo (When determined to be over speed) Phase control (PCK locked) CLV+ H L PWM CLV- L H PWM V/P H H L * Rough servo gain switching Code $A8 $A9 COMMAND DISC 8 Set DISC 12 Set q RES = L For 8 cm discs, the rough servo mode CLV control gain can be set about 8.5 dB lower than the gain used for 12 cm discs. No. 5502-14/35 LC78625E * Phase control gain switching Code $B1 $B2 $B3 $B0 COMMAND CLV phase comparator divisor: 1/2 CLV phase comparator divisor: 1/4 CLV phase comparator divisor: 1/8 No CLV phase comparator divisor used q RES = L The phase control gain can be changed by changing the divisor used by the dividers in the stage immediately preceding the phase comparator. * CLV three-value output Code $B4 $B5 COMMAND CLV three-value output CLV two-value output (the scheme used by previous products) q RES = L The CLV three-value output command allows the CLV to be controlled by a single pin. However, the spindle gain is 6 dB lower when this pin is used, so applications must increase the gain in the servo system. No. 5502-15/35 LC78625E * Internal brake modes Code $C5 $C4 $A3 $CB $CA $CD $CC COMMAND Internal brake on Internal brake off Internal brake CONT Internal brake continuous mode Reset continuous mode TON mode during internal braking Reset TON mode q q q RES = L -- Issuing the internal brake on command ($C5) sets the LC78625E to internal brake mode. In this mode, the disc deceleration state can be monitored from the WRQ pin when a brake command ($06) is executed. -- In this mode the disc deceleration state is determined by counting the EFM signal density in a single frame, and when the EFM signal count falls under four, the CLV- pin is dropped to low. At the same time the WRQ signal, which functions as a brake completion monitor, goes high. When the microprocessor detects a high level on the WRQ signal, it should issue a STOP command to fully stop the disc. In internal brake continuous mode, the CLV- pin high-level output braking operation continues even after the WRQ brake completion monitor goes high. Note that if errors occur in deceleration state determination due to noise in the EFM signal, the problem can be rectified by changing the EFM signal count from four to eight with the internal brake control command ($A3). -- In internal braking TON mode, the TOFF pin is held low during internal brake operations. We recommend using this feature, since it is effective at preventing incorrect detection at the disc mirror surface. Note: If focus is lost during the execution of an internal brake command, the pickup must first be refocussed and then the internal brake command must be reissued. Since incorrect deceleration state determination is possible depending on the EFM signal playback state (e.g., disc defects, access in progress), we recommend using these functions in combination with a microprocessor. 8. Track jump circuit; Pin 19: HFL, pin 20: TES, pin 23: TOFF, pin 24: TGL, pin 25: THLD, pin 28: JP+, pin 29: JP- * The LC78625E supports the two track count modes listed below. Code $22 $23 COMMAND New track count mode (using the TES/HFL combination) Previous track count mode (directly counts the TES signal) RES = L q The earlier track count function uses the TES signal directly as the internal track counter clock. To reduce counting errors resulting from noise on the rising and falling edges of the TES signal, the new track count function prevents noise induced errors by using the combination of the TES and HFL signals, and implements a more reliable track count function. However, dirt and scratches on the disc can result in HFL signal dropouts that may result in missing track count pulses. Thus care is required when using this function. No. 5502-16/35 LC78625E * TJ commands Code $A0 $A1 $11 $12 $31 $52 $10 $13 $14 $30 $15 $17 $19 $1A $39 $5A $18 $1B $1C $38 $1D $1F $16 $0F $8F $8C $21 $20 COMMAND Previous track jump New track jump 1 TRACK JUMP IN #1 1 TRACK JUMP IN #2 1 TRACK JUMP IN #3 1 TRACK JUMP IN #4 2 TRACK JUMP IN 4 TRACK JUMP IN 16 TRACK JUMP IN 32 TRACK JUMP IN 64 TRACK JUMP IN 128 TRACK JUMP IN 1 TRACK JUMP OUT #1 1 TRACK JUMP OUT #2 1 TRACK JUMP OUT #3 1 TRACK JUMP OUT #4 2 TRACK JUMP OUT 4 TRACK JUMP OUT 16 TRACK JUMP OUT 32 TRACK JUMP OUT 64 TRACK JUMP OUT 128 TRACK JUMP OUT 256 TRACK CHECK TOFF TON TRACK JUMP BRAKE THLD period TOFF output mode Reset THLD period TOFF output mode q q RES = L q When the LC78625E receives a track jump instruction as a servo command, it first generates accelerating pulses (period a) and next generates deceleration pulses (period b). The passage of the braking period (period c) completes the specified jump. During the braking period, the LC78625E detects the beam slip direction from the TES and HFL inputs. TOFF is used to cut the components in the TE signal that aggravate slip. The jump destination track is captured by increasing the servo gain with TGL. In THLD period TOFF output mode the TOFF signal is held high during the period when THLD is high. Note: Of the modes related to disc motor control, the TOFF pin only goes low in CLV mode, and will be high during start, stop, and brake operations. Note that the TOFF pin can be turned on and off independently by microprocessor issued commands. However, this function is only valid when disc motor control is in CLV mode. No. 5502-17/35 LC78625E * Track jump modes The table lists the relationships between acceleration pulses, deceleration pulses, and the braking period. Previous Track Jump Mode Item 1 TRACK JUMP IN (OUT) #1 1 TRACK JUMP IN (OUT) #2 1 TRACK JUMP IN (OUT) #3 1 TRACK JUMP IN (OUT) #4 2 TRACK JUMP IN (OUT) 4 TRACK JUMP IN (OUT) 16 TRACK JUMP IN (OUT) 32 TRACK JUMP IN (OUT) 64 TRACK JUMP IN (OUT) 128 TRACK JUMP IN (OUT) 2 track jump period 9 track jump period 18 track jump period 36 track jump period 72 track jump period a 233 s 0.5 track jump period 0.5 track jump period 0.5 track jump period b 233 s 233 s 233 s 233 s None 466 s 7 track jump period 14 track jump period 28 track jump period 56 track jump period 60 ms 60 ms 60 ms 60 ms 60 ms c 60 ms 60 ms This period does not exist. 60 ms; TOFF is low during the C period. a 233 s 0.5 track jump period 0.5 track jump period 0.5 track jump period 1 track jump period 2 track jump period 9 track jump period 18 track jump period 36 track jump period 72 track jump period New Track Jump Mode b 233 s 0.5 track jump period 0.5 track jump period 0.5 track jump period 1 track jump period 2 track jump period 9 track jump period 14 track jump period 28 track jump period 56 track jump period c 60 ms 60 ms This period does not exist. 60 ms; TOFF is low during the C period. See note. 60 ms 60 ms 60 ms 60 ms 60 ms 256 TRACK CHECK TRACK JUMP BRAKE TOFF goes high during the period when 256 tracks are passed over. The a and b pulses are not output. There are no a and b periods. 60 ms 60 ms TOFF goes high during the period when 256 tracks are passed over. The a and b pulses are not output. There are no a and b periods. 60 ms 60 ms Note:* Applications can select whether or not a braking period (period C) is present. Code $F6 selects operation without a braking period, and code $7F selects operation with a 60-ms braking period. The LC78625E defaults to no braking period operation after a reset. * As indicated in the table, actuator signals are not output during the 256 TRACK CHECK function. This is a mode in which the TES signal is counted in the tracking loop off state. Therefore, feed motor forwarding is required. * The servo command register is automatically reset after one cycle of the track jump sequence (a, b, c) completes. * If another track jump command is issued during a track jump operation, the contents of that new command will be executed immediately. * The 1 TRACK JUMP #3 and 2 TRACK JUMP modes (the earlier modes) do not have a braking period (the C period). Since brake mode must be generated by an external circuit, care is required when using this mode. When the LC78625E is used in combination with an LA9230/40 Series LSI, since the THLD signal is generated by the LA9230/40, the THLD pin (pin 25) will be unused, and should be left open. No. 5502-18/35 LC78625E * Tracking brake The chart shows the relationships between the TES, HFL, and TOFF signals during the track jump C period. The TOFF signal is extracted from the HFL signal by TES signal edges. When the HFL signal is high, the pickup is over the mirror surface, and when low, the pickup is over data bits. Thus braking is applied based on the TOFF signal being high when the pickup is moving from a mirror region to a data region and being low when the pickup is moving from a data region to a mirror region. * JP three-value output Code $B6 $B7 COMMAND JP three-value output JP two-value output (earlier scheme) q RES = L The JP three value output command allows the track jump operation to be controlled from a single pin. However, the kick gain is 6 dB lower when this pin is used, so applications must increase the gain in the servo system. * Track check mode Code $F0 $F8 $FF COMMAND Track check in Track check out Two-byte command reset q RES = L The LC78625E will count the specified number of tracks when the microprocessor sends an arbitrary binary value in the range 8 to 254 after issuing either a track check in or a track check out command. No. 5502-19/35 LC78625E Note:*When the desired track count has been input in binary, the track check operation is started by the fall of RWC. * During a track check operation the TOFF pin goes high and the tracking loop is turned off. Therefore, feed motor forwarding is required. * When a track check in/out command is issued the function of the WRQ signal switches from the normal mode subcode Q standby monitor function to the track check monitor function. This signal goes high when the track check is half completed, and goes low when the check finishes. The control microprocessor should monitor this signal for a low level to determine when the track check completes. * If a two-byte reset command is not issued, the track check operation will repeat. That is, to skip over 20,000 tracks, issue a track check 201 command once, and then count the WRQ signal 100 times. This will check 20,000 tracks. * After performing a track check operation, use the brake command to have the pickup lock onto the track. 9. Error flag output; Pin 58: EFLG, pin 62: FSX The FSX signal is generated by dividing the crystal oscillator clock, and is a 7.35 kHz frame synchronization signal. The error correction state for each frame is output from EFLG. The playback OK/NG state can be easily determined from the extent of the high level that appears here. 10. Subcode P, Q, and R to W output circuit; Pin 59: PW, pin 57: SBSY, pin 60: SFSY, pin 61: SBCK PW is the subcode signal output pin, and all the codes, P, Q, and R to W can be read out by sending eight clocks to the SBCK pin within 136 s after the fall of SFSY. The signal that appears on the PW pin changes on the rising edge of SBCK. If a clock is not applied to SBCK, the P code will be output from PW. SFSY is a signal that is output for each subcode frame cycle, and the falling edge of this signal indicates standby for the output of the subcode symbol (P to W). Subcode data P is output on the fall of this signal. SBSY is a signal output for each subcode block. This signal goes high for the S0 and S1 synchronization signals. The fall of this signal indicates the end of the subcode synchronization signals and the start of the data in the subcode block. (EIAJ format) No. 5502-20/35 LC78625E 11. Subcode Q output circuit; Pin 63: WRQ, pin 64: RWC, pin 65: SQOUT, pin 67: CQCK, pin 75: CS Code $09 $89 COMMAND ADDRESS FREE ADDRESS 1 q RES = L Subcode Q can be read from the SQOUT pin by applying a clock to the CQCK pin. Of the eight bits in the subcode, the Q signal is used for song (track) access and display. WRQ will be high only if the data passed the CRC error check and the subcode Q format internal address is 1 (Note 1). The control microprocessor can read out data from SQOUT in the order shown below by detecting this high level and applying CQCK. When CQCK is applied the DSP disables register update internally. The microprocessor should give update permission by setting RWC high briefly after reading has completed. WRQ will fall to low at this time. Since WRQ falls to low 11.2 ms after going high, CQCK must be applied during the high period. Note that data is read out LSB first. Note: 1. These conditions will be ignored if an address free command is sent. This is provided to handle CD-ROM applications. CONT TNO INDEX (POINT)* MIN SEC FRAME ZERO ADR *: Items in parentheses refer to the read-in area. AMIN (PMIN)* /PKMIN ASEC (PSEC)* /PKSEC AFRAME (PFRAME)* /PKFRAME LVM/PKM 16-bit data LVM data/PKM data LVM data/PKM data Note: Normally, the WRQ pin indicates the subcode Q standby state. However, it is used for a different monitoring purpose in track check mode and during internal braking. (See the items on track counting and internal braking for details.) The LC78625E becomes active when the CS pin is low, and subcode Q data is output from the SQOUT pin. When the CS pin is high, the SQOUT pin goes to the high-impedance state. No. 5502-21/35 LC78625E 12. Level meter (LVM) data and peak meter (PKM) data readout Code $2B $2C $2D $2E COMMAND PKM Set (LVM Reset) LVM Set (PKM Reset) PKM mask set PKM mask reset q q RES = L * Level meter (LVM) -- The LVM set command ($2C) sets the LC78625E to LVM mode. -- LVM data is a 16-bit word in which the MSB indicates the L/R polarity and the low-order 15 bits are absolute value data. A one in the MSB indicates left channel data and a zero indicates right channel data. -- LVM data is appended after the 80 bits of subcode Q data, and can be read out by applying 96 clock cycles to the CQCK pin. Each time LVM data is read out the left/right channel state is inverted. Data is held independently for both the left and right channels. In particular, the largest value that occurs between readouts for each channel is held. * Peak meter (PKM) -- The PKM set command ($2B) sets the LC78625E to PKM mode. -- PKM data is a 16-bit word in which the MSB is always zero and the low-order 15 bits are absolute value data. This functions detects the maximum value that occurs in the data, whichever channel that value occurs in. -- PKM data is read out in the same manner as LVM data. However, data is not updated as a result of the readout operation. -- The absolute time for PKM mode subcode Q data is computed by holding the absolute time (ATIME) detected after the maximum value occurred and sending that value. (Normal operation uses relative time.) -- It is possible to set the LC78625E to ignore values larger than the already recorded value by issuing the PKM mask set command, even in PKM mode. This function is cleared by issuing a PKM mask reset command. (This is used in PK search in a memory track.) 13. Mute control circuit Code $01 $02 $03 COMMAND MUTE MUTE MUTE 0 dB -12 dB - dB q RES = L An attenuation of 12 dB (MUTE -12 dB) or full muting (MUTE dB) can be applied by issuing the appropriate command from the table. Since zero cross muting is used, there is minimal noise associated with this function. Zero cross is defined for this function as the top seven bits being all ones or all zeros. 14. Interpolation circuit Outputting incorrect audio data that could not be corrected by the error detection and correction circuit would result in loud noises being output. To minimize this noise, the LC78625E replaces the incorrect data with linearly interpolated data based on the correct data on either side of the incorrect data. More precisely, the LC78625E uses this technique if C2 flags occurred up to three times in a row. If C2 flags occurred four or more times in a row, the LC78625E converges the output level to the muting level. However, when correct data is finally output following four or more C2 flag occurrences, the LC78625E replaces the 3 data items between the data output four items previously and the correct data with linearly interpolated data. No. 5502-22/35 LC78625E 15. Bilingual function Code $28 $29 $2A COMMAND STO CONT Lch CONT Rch CONT RES = L q * Following a reset or when a stereo command ($28) has been issued, the left and right channel data is output to the left and right channels respectively. * When an Lch set command ($29) is issued, the left and right channels both output the left channel data. * When an Rch set command ($2A) is issued, the left and right channels both output the right channel data. 16. De-emphasis; Pin 32: EMPH The pre-emphasis on/off bit in the subcode Q control information is output from the EMPH pin. When this pin is high, the LC78625E internal de-emphasis circuit operates and the digital filters and the D/A converter output deemphasized data. 17. Digital attenuator Digital attenuation can be applied to the audio data by setting the RWC pin high and inputting the corresponding twobyte command to the COIN pin in synchronization with the CQCK clock. Code $81 $82 $83 $84 $85 $86 $87 ATT ATT ATT ATT ATT ATT ATT COMMAND DATA 4STEP 4STEP 8STEP 8STEP 16STEP 16STEP SET UP DOWN UP DOWN UP DOWN RES = L DATA 00H Set (MUTE -dB) * Attenuation setup Since the attenuation level is set to the muted state (a muting of - is specified by an attenuation coefficient of 00H) after the LC78625E is reset, the attenuation coefficient must be directly set to EEH (using the ATT DATA SET command) to output audio signals. Note that the attenuation level can be set to one of 239 values from 00H to EEH. These two-byte commands differ from the two-byte commands used for track counting in that it is only necessary to set RWC once and a two-byte command reset is not required. (See the item on two-byte commands (RWC set once) on page 11.) After inputting the target attenuation level as a value in the range 00H to EEH, sending an attenuator step up/down command will cause the attenuation level to approach the target value in steps of 4, 8, or 16 units as specified in synchronization with rising edges on the LRSY input. However, the ATT DATA SET command sets the target value directly. If a new data value is input during the transition, the value begins to approach the new target value at that point. Note that the UP/DOWN distinction is significant here. No. 5502-23/35 LC78625E ATT DATA Audio output level = 20 log -------------- 100H [dB] For example, the formula below calculates the time required for the attenuation level to increase from 00H to EEH when a 4STEP UP command is executed. Note that the control microprocessor must provide enough of a time margin for this operation to complete before issuing the next attenuation level set command. 238 levels x 4 steps ---------------- * * =21.6 ms 44.1 kHz (LRSY) Note: * Setting the attenuation level to values of EFH or higher is disallowed to prevent overflows in one-bit D/A converter calculations from causing noise. * Mute output; Pin 46: MUTEL, pin 55: MUTER These pins output a high level when the attenuator coefficient is set to 00H and the data in each channel has been zero for a certain period. If data input occurs once again, these pins go low immediately. 18. Digital filter outputs; Pin 33: LRCKO, pin 34: DFORO, pin 35: DFOLO, pin 36: DACKO Data for use with an external D/A converter is output MSB first from DFORO and DFOLO in synchronization with the falling edge of DACKO. These pins are provided so that an external D/A converter can be used if desired. * Although this output is from 8x oversampling filters for normal-speed playback, digital 4x oversampling filters are used in double-speed playback. No. 5502-24/35 LC78625E 19. One-bit D/A converter The LC78625E PWM block outputs a single data value in the range -3 to +3 once every 64fs period. To reduce carrier noise, this block adopts an output format in which each data switching block is adjusted so that the PWM output level does not invert. Also, the attenuator block detects 0 data and enters muting mode so that only a 0 value (a 50% duty signal) is output. This block outputs a positive phase signal to the LCHP (RCHP) pin and a negative phase signal to the LCHN (RCHN) pin. High-quality analog signals can be acquired by taking the differences of these two output pairs using external low-pass filters. The LC78625E includes built-in extraneous radiation suppression resistors (1 k) in each of the LCHP/N and RCHP/N pins. * PWM output format * PWM output example 20. CD-ROM outputs; Pin 42: LRSY, pin 43: CK2, pin 44: ROMXA, pin 45: C2F Although the LC78625E is initially setup to output audio data from the interpolation circuit MSB first from the ROMXA pin in synchronization with the LRSY signal, the circuit can be switched to output CD-ROM data by issuing a CD-ROM XA command. Since this data has not been processed by the interpolation, muting, and other digital circuits, it is appropriate for input to a CD-ROM encoder LSI. CK2 is a 2.1168 MHz clock, and data is output on the CK2 falling edge. However, this clock polarity can be inverted by issuing a CK2 polarity inversion command. C2F is the flag information for the data in 8-bit units. Note that the CD-ROM XA reset command has the same function as the CONT pin (pin 73). The one-bit D/A converter switches to muted mode when a CD-ROMXA command is input. Code $88 $8B $C9 COMMAND CD-ROMXA CONT and CD-ROM XA reset CK2 polarity inversion q RES = L LC78625E CD-ROM encoder LSI (LC895XX) interface No. 5502-25/35 LC78625E 21. Digital output circuit; Pin 56: DOUT This is an output pin for use with a digital audio interface. Data is output in the EIAJ format. This signal has been processed by the interpolation and muting circuits. This pin has a built-in driver circuit and can directly drive a transformer. Code $42 $43 $40 $41 COMMAND DOUT ON DOUT OFF q RES = L q UBIT ON UBIT OFF * The DOUT pin can be locked at the low level by issuing a DOUT OFF command. * The UBIT information in the DOUT data can be locked at zero by issuing a UBIT OFF command. * The DOUT data can be switched to data for which interpolation and muting processing have not been performed by issuing a CD-ROM XA command. 22. Antishock mode; Pin 38: ASDACK, pin 39: ASDFIN, pin 40: ASDEPC, pin 41: ADLRCK, pin 42: LRSY, pin 43: CK2, pin 44: ROMXA, pin 45: C2F * Antishock mode is a mode in which antishock processing is applied to data that has been output once. That data can be returned and output once again as an audio playback signal. It is also possible to use only the audio playback block (the attenuator, 8x oversampling digital filter, and one-bit D/A converter circuits) and thus share the audio playback block with other systems by synchronizing the other system with this LSI's clock. Note that de-emphasis on/off switching is controlled by the level applied to the ASDEPC pin. De-emphasis is turned on by a high level. * The ASDACK (pin 38), ASDFIN (pin 39), ASDEPC (pin 40), and ASLRCK (pin 41) pins can be used as generalpurpose ports (see page 23) if this mode is not used. Code $6C $6B $6F $6E COMMAND ANTIC ON ANTIC OFF q q RES = L DF normal speed on (only in antishock mode) DF normal speed off (only in antishock mode) * It is possible to input the signals from the ROMXA (pin 44), C2F (pin 45), LRSY (pin 42), and CK2 (pin 43) pins to an antishock LSI (the Sanyo LC89151) and re-input the signals output by the antishock LSI to the ASDFIN (pin 39), ASLRCK (pin 41), and ASDACK (pin 38) pins. These signals are then processed by the attenuator, 8x oversampling digital filter, and one-bit D/A converter circuits and output as audio signals. * In antishock systems, the signal-processing block must operate in double-speed playback mode for data output to the antishock LSI, and the audio playback block (the attenuator, 8x oversampling digital filter, and one-bit D/A converter circuits) must operate at normal speed. This means that the control microprocessor must issue both the ANTIC on command ($6C) as well as the DF normal speed on command ($6F). * The ANTIC off command ($6B) clears antishock mode. No. 5502-26/35 LC78625E Note that the LC78625E adds a general-purpose I/O port function that shares the ASDACK, ASDFIN, ASDEPC, and ASLRCK pins. Applications that use the LC78625E with antishock mode turned on must set the P0 (ASDACK), P1 (ASDFIN), P2 (ASDEPC), and P3 (ASLRCK) pins to input mode by issuing a port I/O switching command ($DB0x). But in this case,Pins P0 to P3 cannot be used as input pins. In the default state following a reset, the pins P0 to P3 are set up to be input ports. The only data that can be handled by this circuit as a digital data input interface in antishock mode is data that has a 48fs bit clock rate, a 16-bit data length, an MSB-first format, and a back-packed format. The figure below shows the timing. 23. General-purpose I/O ports; Pin 38: P0, pin 39: P1, pin 40: P2, pin 41: P3 When antichock mode is not used, pins 38 to 41 can be used as the general-purpose I/O ports P0 to P3. After a reset, all these pins are set up as input ports. Unused ports must be either left set up as input ports and connected to 0 V or set up as output ports and left open. Code $DD $DB $DC COMMAND PORT READ PORT I/O SET PORT OUTPUT PORT I SET RES = L The port data can be read out in the order P0, P1, P2, and then P3 from the SQOUT pin is synchronization with falling edges on the CQCK pin by issuing a PORT READ command. This command has the one-byte command format. Another point here is that these pins can be independently set to be used as control output pins with the PORT I/O set command. The ports are selected with the lower 4 bits of the one byte of data. The one byte of data corresponds to P0, P1, P2, and P3 starting with the low order bit. This command has the two-byte command format (RWC set once). One byte data + $DB PORT I/O SET dn = 1 ... Sets Pn to be an output pin. dn = 0 ... Sets Pn to be an input pin. n = 0 to 3 Ports set up to be output pins can be independently set to output either a high or low level. The low order 4 bits of the one byte of data correspond to those ports. The one byte of data corresponds to P0, P1, P2, and P3 starting with the low-order bit. This command has the two-byte command format (RWC set once). One byte data + $DC PORT I/O SET dn = 1 ... Outputs a high level from Pn, which is set up for output. dn = 0 ... Outputs a low level from Pn, which is set up for output. No. 5502-27/35 LC78625E 24. CONT pin; Pin 73: CONT Code $0E $8B COMMAND CONT Set CONT and CD-ROM XA reset RES = L L q The CONT pin goes high when a CONT SET command is issued. 25. Clock oscillator; Pin 77: XIN, pin 78: XOUT Code $8E $8D $CE $C2 $C1 COMMAND OSC ON OSC OFF XTAL 16M Normal-speed playback Double-speed playback q q RES = L q The clock that is used as the time base is generated by connecting a 16.9344 MHz oscillator element between these pins. The OSC OFF command turns off both the VCO and crystal oscillators. Double-speed playback can be specified by microprocessor command. * Connect a 16.9344 MHz oscillator element between the XIN (pin 77) and XOUT (pin 78) pins for double-speed systems. The playback speed can be set by the normal-speed playback and double-speed playback commands. * Recommended crystal and ceramic oscillator elements Load capacitance Cin/Cout (Cin = Cout) 6 pF to 10 pF (10%) 15 pF (10%) 30 pF (Built-in capacitor type) Damping resistor Rd 0 100 (10%) 47 (10%) Manufacturer Citizen Watch Co., Ltd. (crystal oscillator elements) TDK, Ltd. (ceramic oscillator elements) Product No. CSA-309 (16.9344 MHz) FCR 16.93M2G (16.93 MHz) FCR 16.93MCG (16.93 MHz) Since the conditions for the load capacitors Cin and Cout used vary with the printed circuit board, this circuit must be tested on the printed circuit board actually used. 26. 16M and 4.2M pins; Pin 71: 16M, pin 72: 4.2M In normal- and double-speed playback modes, the 16M pin buffer outputs the 16.9344 MHz external crystal oscillator 16.9344 MHz signal. The 4.2M pin supplies an LA9230/40 Series LSI system clock, continuously outputting a 4.2336 MHz signal. When the oscillator is turned off both these pins will be fixed at either high or low. No. 5502-28/35 LC78625E 27. Reset circuit; Pin 68: RES When power is first applied, this pin should be briefly set low and then set high. This will set the muting to - dB and stop the disc motor. CLV servo related Muting control Subcode Q address condition Laser control CONT Track jump mode Track count mode Digital attenuator OSC Playback speed Antishock mode Digital filter normal speed Note: START 0 dB Address 1 ON (L) H Previous Previous DATA 0 ON Normal speed ON ON STOP -12 dB Address Free OFF (H) L New New DATA 00H to EEH OFF Double speed OFF OFF BRAKE - CLV Setting the RES pin low sets the LC78625E to the settings enclosed in boxes in the table. 28. Sound output function for set adjustment during manufacturing; Pin 30: DEMO The DEMO pin can be used when the LC78625E is used in combination with an LA9210M or LA9211M. By setting this pin high, muting can be set to 0 dB, the disc motor can be set to CLV, and a focus start operation can be performed, even without issuing any commands from the control microprocessor. Also, since the LASER pin becomes active, if the mechanism and servo systems are complete, an EFM signal can be acquired with only this equipment, and an audio signal can be produced without the presence of a microprocessor. However, since the digital attenuation is set to 100H, this technique is not appropriate for evaluating audio quality. No. 5502-29/35 LC78625E 29. Other pins; Pin 2:TAI, pin 80: TEST1, pin 12: TEST2, pin 26: TEST3, pin 31: TEST4, pin 74: TEST5 These pins are used for testing the LSI's internal circuits. Although the pins TAI and TEST1 to TEST5 have built-in pull-down resistors, they should be connected to ground (0 V) for safety. 30. Circuit Block Operating Descriptions * RAM address control The LC78625E incorporates an 8-bit x 2k-word RAM on chip. This RAM has an EFM demodulated data jitter handling capacity of 4 frames implemented using address control. The LC78625E continuously checks the remaining buffer capacity and controls the data write address to fall in the center of the buffer capacity by making fine adjustments to the frequency divisor in the PCK side of the CLV servo circuit. If the 4 frame buffer capacity is exceeded, the LC78625E forcibly sets the write address to the 0 position. However, since the errors that occur due to this operation cannot be handled with error flag processing, the IC applies muting to the output for a 128 frame period. Position -4 or lower -3 -2 -1 0 +1 +2 +3 +4 or greater Divisor or Handling Forcibly moves to 0 589 589 589 588 587 587 587 Forcibly moves to 0 Decreasing divisors Standard divisor Advancing divisors * C1 and C2 error correction The LC78625E writes EFM demodulated data to internal RAM to compensate for jitter and then performs the following processing with uniform timing based on the crystal oscillator clock. First, the LC78625E performs C1 error checking and correction in the C1 block, determines the C1 flags, and writes the C1 flag register. Next, the LC78625E performs C2 error checking and correction in the C2 block, determines the C2 flags, and writes data to internal RAM. C1 Check No errors Single error Dual errors Three or more errors Correction and Flag Processing Correction not required * flags cleared Correction performed * flags cleared Correction performed * flags set Correction not possible * flags set C2 Check No errors Single error Dual errors Three or more errors Correction and Flag Processing Correction not required * flags cleared Correction performed * flags cleared C1 flags referenced. Note 1 C1 flags referenced. Note 2 Note: 1. If the positions of the errors determined by the C2 check agree with the those specified by the C1 flags, the correction is performed and the flags are cleared. However, if the number of C1 flags is 7 or higher, C2 correction may fail. In this case correction is not performed and the C1 flags are taken as the C2 flags without change. Error correction is not possible if one error position agrees and the other does not. Furthermore, if the number of C1 flags is 5 or under, the C1 check result can be seen as unreliable. Accordingly, the flags will be set in this case. Cases where the number of C1 flags is 6 or more are handled in the same way, and the C1 flags are taken as the C2 flags without change. When there is not even one agreement between the error positions, error correction is, of course, impossible. Here, if the number of C1 flags was 2 or under, data that was seen as correct after C1 correction is now seen as incorrect data. The flags are set in this case. In other cases, the C1 flags are taken as the C2 flags without change. 2. When data is determined to have three or more errors and be uncorrectable, correction is, of course, impossible. Here, if the number of C1 flags was 2 or under, data that was seen as correct after C1 correction is now seen as incorrect data. The flags are set in this case. In other cases the C1 flags are taken as the C2 flags without change. No. 5502-30/35 LC78625E Command Summary Table Blank entry: Illegal command, #: Command added since or changed from the LC78620/1E specifications, 5: Latching commands (mode setting commands), q: Commands shared with an ASP (LA9230M/31M or other processor), Items in parentheses are ASP commands (provided for reference purposes) $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F 5CONT SET 5TRACKING OFF (ADJ. RESET) 5MUTE 0 dB 5MUTE -12 dB 5MUTE -dB 5DISC MTR START 5DISC MTR CLV 5DISC MTR BRAKE 5DISC MTR STOP q FOCUS START #1 5ADDRESS FREE 5LASER ON $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2A $2B $2C $2D $2E $2F 5STO CONT 5LCH CONT 5RCH CONT 5PKM SET 5LVM SET 5PKM MSK SET 5PKM MSK RESET 5TJ TOFF "L" 5TJ TOFF "H" 5New TRACK COUNT 5Old TRACK COUNT $40 $41 $42 $43 $44 $45 $46 $47 $48 $49 $4A $4B $4C $4D $4E $4F 5UBIT ON 5UBIT OFF 5DOUT ON 5DOUT OFF $60 $61 $62 $63 $64 $65 $66 $67 $68 $69 $6A $6B $6C $6D $6E $6F 5DF normal speed off 5DF normal speed on 5ANTIC "OFF" 5ANTIC "ON" $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1A $1B $1C $1D $1E $1F 2TJ IN 1TJ IN 1TJ IN 4TJ IN 16TJ IN 64TJ IN 256TC 128TJ IN 2TJ OUT 1TJ OUT #1 1TJ OUT #2 4TJ OUT 16TJ OUT 64TJ OUT #1 #2 $30 $31 $32 $33 $34 $35 $36 $37 $38 $39 $3A $3B $3C $3D $3E 32TJ IN 1TJ IN #3 $50 $51 $52 $53 $54 $55 $56 $57 1TJ IN #4 $70 $71 $72 $73 $74 $75 $76 $77 $78 $79 1TJ OUT #4 $7A $7B $7C $7D $7E $7F 32TJ OUT 1TJ OUT #3 $58 $59 $5A $5B $5C $5D $5E $5F 128TJ OUT $3F Continued on next page. No. 5502-31/35 LC78625E Continued from preceding page. $80 $81 $82 $83 $84 $85 $86 $87 $88 $89 $8A $8B $8C $8D $8E $8F $90 $91 $92 $93 $94 $95 $96 $97 $98 $99 $9A $9B $9C $9D $9E $9F * 5ATT DATA SET 5ATT 4STP UP 5ATT 4STP DWN 5ATT 8STP UP 5ATT 8STP DWN 5ATT 16STP UP 5ATT 16STP DWN 5CDROMXA 5ADDRESS "1" 5LASER OFF 5CONT, ROMXA RST TRACK JMP BRK 5OSC OFF 5OSC ON 5TRACKING ON (5F. OFF. ADJ. ST) (5F. OFF. ADJ. OFF) (5T. OFF. ADJ. ST) (5T. OFF. ADj. OFF) (5LSR. ON) (5LSR. OF/F. SV. ON) (5LSR. OF/F. SV. OF) (5SP. 8CM) (5SP. 12CM) (5SP. OFF) (5SLED. ON) (5SLED. OFF) (5EF. BAL. START) (5T. SERVO. OFF) (5T. SERVO. ON) $A0 $A1 $A2 $A3 $A4 $A5 $A6 $A7 $A8 $A9 $AA $AB $AC $AD $AE $AF $B0 $B1 $B2 $B3 $B4 $B5 $B6 $B7 $B8 $B9 $BA $BB $BC $BD $BE $BF 5CLV-PH 1/1 mode 5CLV-PH 1/2 mode 5CLV-PH 1/4 mode 5CLV-PH 1/8 mode 5CLV3ST output ON 5CLV3ST output OFF 5JP3ST output ON 5JP3ST output OFF *PLL DIV OFF *PLL DIV ON 5DISC 8 SET 5DISC 12 SET 5Old TRACK JMP 5New TRACK JMP FOCS START #2 5Internal BRKE CONT $C0 $C1 $C2 $C3 $C4 $C5 $C6 $C7 $C8 $C9 $CA $CB $CC $CD $CE $CF $D0 $D1 $D2 $D3 $D4 $D5 $D6 $D7 $D8 $D9 $DA $DB $DC $DD $DE $DF *PORT OP-ED SET *PORT DATA SET * 5CK2 polarity inverted 5Internal BRK-DMC "L" 5Internal BRK-DMC "H" 5Internal BRK TOFF 5Internal BRK TON 5XTAL * 5Internal BRK OFF 5Internal BRK ON 5Double speed 5Normal speed $E0 $E1 $E2 $E3 $E4 $E5 $E6 $E7 $E8 $E9 $EA $EB $EC $ED $EE $EF $F0 $F1 $F2 $F3 $F4 $F5 $F6 $F7 $F8 $F9 $FA $FB $FC $FD $FE $FF q NOTHING 5q 2BYTE CMD RST q *No C period set for 2TJ mode *C period present set for 2TJ mode 5q TRACK CHECK OUT q (2BYTE DETECT) 5Command noise off 5Command noise on 5q TRACK CHECK IN q (2BYTE DETECT) Note: $AC is a supplementary command for low-voltage operation. No. 5502-32/35 LC78625E Sample Application Circuit No. 5502-33/35 LC78625E Differences between the LC78625E and the LC78620E LC78625E Item Content of change Bilingual processing for antishock input data is now possible in antishock mode. The same bilingual control commands as those used in the LC78620E are used. Bilingual function (Command code) $28: $29: $2A: (Command mode) Stereo output (Initial state after a reset) Both left and right are output to the left channel Both left and right are output to the right channel LC78620E A bilingual processing function is not provided for antishock input data in antishock mode. The de-emphasis filters are turned on or off by the input level on the ASDEPC/P2 pin in antishock mode. De-emphasis function (ASDEPC/P2) (De-emphasis filter) The on/off state of the de-emphasis filter cannot be controlled from an external pin. High level applied: On Low level applied: Off A command was added that allows the presence or absence of a braking period (the C period) to be selected during two-track jumps (new track jump mode only). Track jump function (Command code) $F6: $F7: (C period) None (Initial state after a reset) Present (60 ms) There is no C period during two-track jumps (in new track jump mode). When antishock mode is not used, the antishock input pins can be used as general-purpose I/O pins. To support this functionality, the pin names were changed and commands were added. (These command codes are identical to those on the LC78622E.) * Pin name changes: (LC78625E) ASDACK/P0 ASDFIN/P1 ASDEPC/P2 ADLRCK/P3 General-purpose ports added * Added commands: $DB0X: I/O switching command (2 bytes) $DC0Y: Port output data setup command (2 bytes) $DD: Port input command (1 byte) Here X and Y represent 4-bit data items that control P0, P1, P2, and P3 in order starting with the low order bit. X: A zero specifies input and a one specifies output. (These pins default to input after a reset.) Y: A zero specifies a low-level output, and a one specifies a high-level output. The frequency range was increased over that supported by the LC78620E. (The range is identical to that of the LC78622E) This resulted in a change in the value of the resistor used on the FR pin: 1.2 k. Addition of a supplementary command for low-voltage operation. PLL circuit $AC: PLL DIVIDER OFF (Low-voltage operation supplementary command) $AD: PLL DIVIDER ON (Initial state after a reset) No such commands are supported. (LC78620E) ASDACK ASDFIN ASDFIR ASLRCK There are no general-purpose ports. VCO circuit A 5.1 k resistor is connected to the FR pin. No. 5502-34/35 LC78625E CD Digital Signal Processor LSI Functional Comparison Type No. LC7860KA Function EFM-PLL 16KRAM Digital outputs Interpolation Zero cross muting Level meter peak search Bilingual function Digital attenuator 2 fs 4 fs 8 fs Digital de-emphasis One-bit D/A converter LC7861NE LC7861KE LC7867E LC7868E LC7868KE LC7869E LC78681E LC78681KE LC78620E LC78621E LC78625E Built-in VCO q q 4 q q q q -- -- q q q When used along When used along When used along When used along When used along When used along with an analog ASP. with an analog ASP. with an analog ASP. with an analog ASP. with an analog ASP. with an analog ASP. External x 2 x x x x q -- -- x x q q 4 q x x x q -- -- x x q q 4 q x x x -- -- -- x x q q 4 q q q x -- q -- q x q q 4 q q q x -- -- q q x q q 4 q q q x -- -- -- x x s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of February, 1997. Specifications and information herein are subject to change without notice. No. 5502-35/35 |
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